Delay-locked loops are for instance used in the context of Digital Pulse-Width Modulation (DPWM). DPWM in turn is for instance deployed in energy management hardware, where a switching regulator (e.g. a Switched-Mode Power Supply, SMPS) generates from the battery voltage the voltage level used by a load (for instance a processor of an electronic device). Therein, DPWM is applied in a digital feedback loop of the switching regulator.
Architectures for DPWM targeting digital control of high-frequency switching DC-DC power converters are presented in document “Digital pulse-width modulator architectures” by Syed, E. Ahmen, E. Alarcon, D. Maksimovic, IEEE Power Electronics Specialists Conference, vol. 6, pp. 4689-4695, June 2004, the contents of which document are incorporated herein by reference.
Digital feedback with DPWM usually consumes a lot of power, when the switching frequency (the frequency at which switches are operated to generate the DPWM) and the high-frequency clock used to generate the DPWM are high. However, if a high Direct Current (DC) output voltage accuracy is desired, generally an even higher high-frequency clock is required in current applications based on the system parameters, thus further increasing power consumption of the DPWM.